Tamer Cakici, Ph.D.
Affiliations: | 2007 | Electrical and Computer Engineering | Purdue University, West Lafayette, IN, United States |
Area:
Electronics and Electrical EngineeringGoogle:
"Tamer Cakici"Parents
Sign in to add mentor| Kaushik Roy | grad student | 2007 | Purdue | |
| (Exploiting independent gate technology in Multiple-Gate silicon CMOS circuit design.) | ||||
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Publications
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| Cakici T, Keejong K, Roy K. (2007) FinFET based SRAM design for low standby power application Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 127-132 |
| Hwang ME, Cakici T, Roy K. (2007) Process tolerant β-ratio modulation for ultra-dynamic voltage scaling Proceedings -Design, Automation and Test in Europe, Date. 1550-1555 |
| Roy K, Mahmoodi H, Mukhopadhyay S, et al. (2006) Double-gate SOI devices for low-power and high-performance applications Proceedings of the Ieee International Conference On Vlsi Design. 2006: 445-452 |
| Cakici T, Mahmoodi H, Mukhopadhyay S, et al. (2005) Independent gate skewed logic in double-gate SOI technology Proceedings - Ieee International Soi Conference. 2005: 83-84 |
| Cakici T, Bansal A, Roy K. (2003) A Low Power Four Transistor Schmitt Trigger for Asymmetric Double Gate Fully Depleted SOI Devices Ieee International Soi Conference. 21-22 |
| Cakici T, Roy K. (2002) Current mirror evaluation logic: A new circuit style for high fan-in dynamic gates European Solid-State Circuits Conference. 395-398 |